PMTS ASIC Digital Design IP ENGINEERING

Overview

Lead the architecture implementation, microarchitecture development, and RTL design of high-performance processor cores and subsystem components, driving complex SoC development programs from concept through silicon bring-up.

What you'll do

• Develop and implement microarchitecture for CPU cores, cache subsystems, memory management units (MMU), interconnects, and system controllers.
• Translate architectural specifications into high-quality RTL designs using Verilog/SystemVerilog.
• Define and review detailed design specifications, block-level architectures, and implementation strategies.
• Drive performance optimization, power reduction, and area-efficient design methodologies.
• Analyze and resolve complex design trade-offs involving latency, throughput, and scalability.
• Lead critical processor design initiatives across multiple functional blocks.
• Mentor junior and senior engineers on microarchitecture, RTL coding practices, and design methodologies.
• Conduct architecture, microarchitecture, and RTL design reviews.
• Establish design guidelines and best practices across the organization.
• Influence roadmap and technology decisions for future processor generations.
• Partner with architects to evaluate new features and enhancements.
• Work closely with verification teams to define verification plans and close coverage.
• Support synthesis, timing closure, low-power implementation, and physical design activities.
• Collaborate with DFT teams to ensure manufacturability and testability.
• Support silicon bring-up, debug, characterization, and production ramp activities.
• Conduct design performance analysis and bottleneck identification.
• Drive microarchitectural enhancements to improve IPC, memory latency, and system efficiency.
• Analyze workload behavior and benchmark performance.
• Participate in power-performance-area (PPA) optimization efforts.

What you'll need

• Bachelor's or master's degree in electrical engineering, computer engineering, or related field.
• 12+ years of experience in processor, CPU, DSP, or complex SoC digital design.
• Deep understanding of processor microarchitecture, including pipeline design, cache architectures, branch prediction, memory hierarchy, MMU/TLB designs, interrupt and exception handling, and coherency protocols.
• Expert-level RTL design experience using Verilog/SystemVerilog.
• Strong understanding of synthesis, timing analysis, CDC, RDC, and low-power design techniques.
• Experience with industry-standard EDA tools and design flows.
• Strong debugging and problem-solving skills.

Nice to have

• Experience with RISC-V, ARM, MIPS, ARC, or custom CPU architectures.
• Knowledge of multi-core and heterogeneous computing systems.
• Experience in AI/ML acceleration, vector processing, or advanced computing architectures.
• Experience with performance modeling and architectural simulation.
• Silicon bring-up and post-silicon debug experience.
• Exposure to safety-critical designs (ISO 26262, DO-254) is a plus.

Details

• Location: Hyderabad, Telangana, India.
• Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.