Digital Design Engineer, DMTS/SMTS/MTS

Overview

Design, develop, and deliver RTL for complex DRAM, memory, and mixed-signal digital blocks. Drive front-end ASIC design projects from architecture and specification through implementation handoff while meeting performance, power, area, quality, and schedule targets.

What you'll do

• Design, develop, and deliver high-quality RTL for complex DRAM, memory, and mixed-signal digital blocks.
• Drive projects from architecture and specification through implementation handoff while meeting performance, power, area, and quality targets.
• Own front-end ASIC design activities, including RTL development, linting, CDC/RDC verification, functional validation, logic synthesis, static timing analysis, timing constraint definition, and timing closure across multi-mode, multi-corner operating conditions.
• Develop, maintain, and optimize design constraints, including clock definitions, timing exceptions, I/O constraints, UPF-based power intent, and low-power implementation methodologies.
• Collaborate with architecture, verification, circuit design, and physical implementation teams to resolve integration challenges and ensure successful product execution.
• Analyze synthesis and timing reports, identify critical bottlenecks, and drive design improvements.
• Contribute to design methodologies, automation frameworks, and RTL-to-GDS implementation flows.
• Apply CMOS digital and mixed-signal concepts, Verilog/SystemVerilog, and industry-standard EDA tools to develop scalable and reliable silicon solutions.
• Demonstrate automation, AI-assisted engineering technologies, and generative AI tools to enhance design efficiency, collaboration, and engineering effectiveness.
• Demonstrate problem-solving, communication, and collaboration skills while mentoring peers and contributing to technical excellence and innovation.

What you'll need

• Bachelor’s or Master’s degree, or equivalent experience, in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
• 10+ years of relevant ASIC or SoC design experience, with significant ownership of complex front-end design projects.
• Advanced proficiency in RTL design and microarchitecture development using Verilog and SystemVerilog.
• Validated ability to take designs from architecture and specification through RTL implementation, verification support, synthesis, timing closure, and implementation handoff.

Nice to have

• For a principal or senior technical-lead position, 12–15+ years may be preferred.

Details

• Location: Hyderabad, Telangana, India, or Bengaluru, Karnataka, India.