Principal Logic Design Engineer

Overview

Lead the architecture, microarchitecture, RTL implementation, integration, and silicon bring-up of complex connectivity IPs and subsystems.

What you'll do

• Lead RTL and microarchitecture development for complex connectivity IPs and subsystems.
• Translate specifications and system requirements into hardware architecture.
• Design high-performance, scalable logic for controllers and subsystems.
• Develop and review SystemVerilog/Verilog RTL.
• Drive flow control, ordering, buffering, arbitration, error handling, and reliability mechanisms.
• Collaborate with verification, SoC integration, and physical design teams.
• Lead technical reviews, mentor senior engineers, and support post-silicon debugging.

What you'll need

• 10+ years of experience.
• Extensive experience with connectivity IPs such as PCIe, UALink, Ethernet, CXL, or UCIe.
• Strong RTL design experience using SystemVerilog or Verilog.
• Deep knowledge of PCIe architecture and protocol.
• Understanding of high-speed data paths, FIFOs, arbitration, flow control, and error handling.
• Experience with simulation, lint, CDC, synthesis, and timing considerations.
• Strong debugging and problem-solving skills.

Nice to have

• Experience working in switching silicon.
• Experience across the full cycle from concept to silicon production.

Details

• Location: Bengaluru, Karnataka, India.