SoC RTL Design- Sr Staff Engineer

Overview

Sr Staff Engineer role in SoC RTL design and integration, requiring hands-on experience in RTL coding and SoC-level work.

What you'll do

• Develop logic/micro-architecture and perform RTL coding for SoCs.
• Work on SoC design and integration activities for SoCs.
• Create constraint development and support timing closure.
• Collaborate with SoC verification and validation teams for pre/post-silicon debug.
• Contribute to Low power SoC design efforts.
• Participate in pad ring creation and coordinate with chip-level floorplan teams.

What you'll need

• Minimum education includes Bachelors with 2+ years hardware engineering experience, or Masters with 1+ year, or PhD.
• Hands-on experience in Logic design/micro-architecture/RTL coding.
• Hands-on SoC design and integration experience.
• Verilog/System-Verilog experience is required.
• Knowledge of AMBA protocols (AXI, AHB, APB), SoC clocking/reset/debug architecture and peripherals (USB, PCIE, SDCC).
• Experience in constraint development and timing closure.

Nice to have

• 12+ years of experience in digital front-end ASIC/RTL design.
• Knowledge of memory controller designs and microprocessors.
• Experience in creating pad ring and working with chip level floorplan team.

Details

• Location: Bangalore, India.