Principal Logic Design Engineer - UALink IP/Subsystem

Overview

Principal Logic Design Engineer to lead RTL and microarchitecture development for UALink-based IP/subsystems.

What you'll do

• Lead architecture and RTL development for UALink IP/subsystems.
• Translate protocol and system requirements into scalable hardware architecture.
• Design high-bandwidth, low-latency data paths and control logic.
• Develop flow control, ordering, buffering, arbitration, error handling, and reliability mechanisms.
• Define interfaces between UALink and other SoC/interconnect components.
• Develop and review SystemVerilog RTL and drive optimization for performance, power, area, and latency.

What you'll need

• 10–15 years of experience.
• Strong experience in RTL and microarchitecture development.
• Experience with high-speed interconnects and/or coherent fabrics.
• Proficiency in SystemVerilog/Verilog.
• Strong understanding of CDC, reset architecture, performance, and hardware design methodology.

Nice to have

• Preferred: Direct UALink experience.
• Preferred: Experience with PCIe, CXL, CCIX, CHI, Ethernet, or similar protocols.
• Preferred: Experience in AI/accelerator or high-performance compute systems.

Details

• Location: Bengaluru, Karnataka, India.