ASIC Engineering Technical Leader (RTL Design/SOC | 8- 14 Years)

Overview

Lead ASIC engineering for Cisco's SiliconOne team, owning RTL design and the SoC development cycle from specification through tape-out and lab validation on high-performance, high-volume products.

What you'll do

• Understand the architecture in depth and identify problems and solutions.
• Work across all aspects of implementation: specification, design, timing analysis, and power optimization.
• Optimize logic for low power and area, and highlight issues and standard methodologies for power and area optimization.
• Document and improve standard methodologies to make the product successful.

What you'll need

• BS/MS with 11+ years (BS) or 9+ years (MS) of hands-on experience in large-scale, high-performance ASIC RTL development.
• Hands-on skills in Verilog, SystemVerilog, VCS, Spyglass, CDC and formal verification.
• Experience in system debug, SW/HW bring-up, and system validation of silicon towards FCS.
• Gate-level understanding of RTL and synthesis.
• Programming/scripting skills in Python, C, C++ or Perl.
• Good written/verbal interpersonal and leadership skills.

Nice to have

• Experience in architecture and definition of high-scale, high-performance ASICs.
• Validated experience in implementation: specification, RTL design, lint, CDC, timing analysis, formal verification, and system testing.
• Validated experience in flow automation (scripting, Makefiles, etc.) and establishing team guidelines.
• Validated leadership to accurately describe issues/improvements and lead the team to on-time completion.

Details

• Location: Bangalore, India.