Principal Engineer – Design Engineering

Overview

Principal Engineer in the Communications Business Unit (CBU) Product Development team, responsible for the design and implementation of digital integrated circuits at block or top level for networking, connectivity and edge compute semiconductor devices.

What you'll do

• Contribute to the microarchitecture of communication semiconductor devices in partnership with team leads, mentors and device architects
• Design digital circuits based on leading-edge industry standards and market requirements
• Implement designs in System Verilog RTL code utilizing low-power design principles
• Synthesize designs into logic gates taking advantage of industry-leading tools and flows
• Provide floor-planning guidance and support to physical design/layout teams
• Integrate digital and analog circuits with Design-for-Test (DFT) techniques
• Verify physical timing specifications through Static Timing Analysis (STA)
• Support products from Specification through to Production in collaboration with Physical Design, Validation, Applications, Software/Firmware, Product Marketing and Production Engineering
• Develop areas of technical expertise to contribute to the wider team beyond individual deliverables or responsibilities

What you'll need

• Bachelor's or Master's Degree in Electrical Engineering or Computer Engineering
• 8+ years related experience
• Excellent analytical and debugging skills and the ability to proactively solve issues
• Proven ability to thrive on, learn and adapt to new methodologies and technologies
• Coding expertise in one or more of SystemVerilog/Verilog or VHDL
• Experience using one or more of Tcl/Perl/Python, C/C++, XML
• Excellent verbal and written communication skills in English
• Experience with Lint, CDC, formal verification, logic synthesis, and static timing analysis
• Understanding of physical design interactions, including timing, power, and congestion considerations
• Knowledge of DFT, including scan, testability considerations, and DFT sign-off interactions
• Proficiency in scripting languages such as Tcl, Perl, and/or Awk

Nice to have

• Experience with Synopsys or Cadence tool flows for synthesis, verification or STA
• Experience with 28nm and smaller silicon process technologies

Details

• Location: India - Bangalore
• Travel time: 0% - 25%