Principal Engineer - Design

Overview

The Principal Engineer - Design will join Microchip’s Data Center Solutions business unit to drive architecture, design excellence, and methodology innovation for complex data center-class ASICs. The role supports high-performance silicon solutions used by server and storage OEMs and hyperscale data centers.

What you'll do

• Lead architecture and micro-architecture definition for complex IPs, subsystems, or full-chip designs.
• Drive end-to-end RTL design execution, from concept through synthesis, sign-off, and silicon bring-up support.
• Serve as a technical authority for digital design, ensuring high standards in quality, performance, power, and area (PPA).
• Resolve complex, cross-domain design and EDA tool challenges impacting schedule or silicon quality.
• Collaborate closely with verification, physical design, DFT, system, and product teams to ensure robust and predictable delivery.
• Guide low-power, high-performance design strategies suitable for data center workloads.
• Influence protocol and platform roadmap decisions, particularly in PCIe, CXL, NVMe, SAS, and related interconnects.
• Mentor and technically guide engineers, providing architectural reviews and design direction.

What you'll need

• 10+ years of experience in ASIC or SoC digital design.
• Bachelor degree in Electronics or Electrical Engineering minimum.
• Strong expertise in SystemVerilog RTL design and micro-architecture development.
• Proven success delivering multiple complex tape-outs in high-performance or data center-class silicon.
• Deep hands-on experience with Lint, CDC, formal verification, logic synthesis, and static timing analysis.
• Strong understanding of physical design interactions, including timing, power, and congestion considerations.
• Solid experience with low-power design methodologies and flows.
• Mandatory knowledge of DFT, including scan, testability considerations, and DFT sign-off interactions.
• Proficiency in scripting languages such as Tcl, Perl, and/or Awk.
• Hands-on experience with high-speed protocols such as PCIe, CXL, NVMe, SAS/SATA, or similar serial interfaces.
• Experience in AI-driven workflows to accelerate AI development.

Nice to have

• Hands-on experience with Cadence-based ASIC design environments is an asset.

Details

• Location: Bangalore, India.
• Travel time: 0% - 25%.