Lead Principal Engineer Design

Overview

Lead the physical design and timing closure of low-power SoCs targeted at IoT and MCU markets as a Lead Principal Engineer Design within Infineon's Research & Development team.

What you'll do

• Lead physical design and timing closure of low-power SoCs targeted for IoT/MCU markets.
• Achieve die area, performance and power goals for hierarchical blocks and the top level.
• Drive physical design implementation, including package co-design, floorplanning, power grid design and signoff, place and route, timing closure and physical verification checks.
• Influence tools, flows and methodology activities to improve quality of results (QoR).
• Interact with cross-functional team members to improve design, methodology and process aspects.

What you'll need

• Deep and broad understanding of physical design and timing convergence of hierarchical SoCs.
• Expert user of industry-standard tools and flow/automation for physical design and signoff.
• In-depth knowledge of process technologies and associated physical design challenges.
• Deep understanding of low-power design techniques and implementation methodologies.

Details

• Location: Bangalore BTP.