Senior Staff Engineer Digital Design

Overview

Drive physical design and timing closure for complex, low-power SoCs targeted at IoT and MCU markets, supporting hierarchical blocks and top-level implementation.

What you'll do

• Drive die area, performance, and power goals for hierarchical blocks and top-level designs.
• Perform physical design implementation across floor planning, IO planning, package co-design, power grid design, place and route, clock tree synthesis, and timing closure.
• Perform static and dynamic IR drop analysis and physical verification checks.
• Implement SoCs with multiple voltage islands, power islands, and other power reduction techniques.
• Drive flow and methodology activities to improve QoR.

What you'll need

• Bachelor's or Master's degree with specialization in VLSI design.
• 8+ years of hands-on experience in physical design and timing closure of SoCs.
• Experience with industry-standard tools for physical design and signoff.
• Experience with scripting languages including shell, Perl, and Tcl, and Make flow.
• Understanding of 40nm, 28nm, and 22nm technologies and associated physical design challenges.
• Be a good team player and have a desire to learn and explore.
• Strong commitment and determination in the area of expertise.
• Be well organized, methodical, and detail oriented.
• Take initiatives and overcome challenges through creativity and innovation.
• Coordinate with colleagues and actively share expertise with others.
• Share information comprehensively and effectively.

Details

• Location: Bangalore BTP, India.