Backend Physical Design Engineer

Overview

Backend Physical Design Engineer role applying and leading Broadcom's design methodology and milestone flow to achieve right-first-time silicon, with layout activities at block and chip level.

What you'll do

• Understand SoC top-down and bottom-up physical design integration in 5nm and lower technologies.
• Deep functional knowledge of P&R flows; quickly learn and adapt to internal flows.
• Implement timing and functional ECO.
• Perform P&R, extraction, physical verification, and work towards STA closure.
• Build automation flows where needed, or adapt existing flows for re-use.
• Use Cadence, Synopsys or Mentor EDA tools for P&R, PV, STA and ECO.
• Lead by example and clearly know the requisites for executing the job.
• Bring tangible improvement in turnaround time (TAT) with better quality.

What you'll need

• MSEE/MSCS with 6+ years of experience, or BSEE/BSCS with 8+ years of experience.
• Deep understanding of backend digital design flow.
• Proficient in timing constraints and physical constraints.
• Proficient in handling EDA tools across floorplan, partition, placement, CTS and route stages for SoC top.
• Proficient with backend EDA tools: Genus, Innovus, Quantus, Tempus, DC, Star-RCXT, PT, PrimeRail, Voltus, Redhawk.
• Proficiency in Tcl and Perl.
• Needs to be automation savvy with high expertise in one industry programming language.
• Experience in layout of blocks and chip level, including floor-planning, partitioning, placement, clock tree synthesis, routing and physical verification.
• Excellent analytical skills.
• Ability to collaborate in a multi-functional environment, cross-site or cross-time zone.

Details

• Location: Bangalore Electronic City, India.