NPU Physical Design Engineer (Lead/Staff/Sr Staff)

Overview

Qualcomm is seeking an NPU Physical Design Engineer (Lead/Staff/Sr Staff) to implement PNR for the Qualcomm Hexagon NPU, working on the latest technology nodes.

What you'll do

• Take complete ownership of PNR implementation, including floorplanning, placement, CTS, post-route and related stages, on latest nodes.
• Apply signoff knowledge (STA, power analysis, FV, low power verification, PV, etc.).

What you'll need

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience, OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience, OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
• 7+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm).
• Good hands-on experience on floorplanning, PNR and STA flows.
• Good knowledge of placement/clock tree synthesis (CTS) and optimization.
• Good understanding of signoff domains, including LEC/CLP/PDN knowledge.
• Good knowledge of Unix/Linux and Perl/TCL fundamentals/scripting.
• Quick learner with good analytical and problem solving skills.

Details

• Location: Bangalore, India.