SoC Physical Design

Overview

Lead end-to-end physical design implementation for large-scale SoCs and complex subsystems, from architecture definition through successful tapeout.

What you'll do

• Lead end-to-end physical design implementation for large-scale SoCs and complex subsystems, driving projects from architecture definition to successful tapeout.
• Own full-chip and subsystem physical design strategy including Floorplanning, Power Planning (PDN), Placement, CTS, Routing, Timing Closure, Signal Integrity, and Physical Verification.
• Drive PPA (Performance, Power, Area) optimization and signoff closure across advanced process nodes.
• Define and enhance physical design methodologies, automation flows, and best practices to improve design efficiency and quality.
• Lead cross-functional collaboration with Architecture, RTL, STA, DFT, Package, CAD, Technology, and Product Engineering teams to achieve aggressive silicon schedules.
• Resolve complex design challenges involving timing convergence, congestion, IR/EM, noise, reliability, and manufacturability.
• Provide technical leadership during tapeout planning and execution, ensuring high-quality silicon delivery.
• Mentor and guide junior engineers, driving technical excellence across the organization.
• Influence future design methodologies and contribute to strategic technology roadmap decisions.

What you'll need

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience, OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience, OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
• 3+ years of hands-on experience in ASIC/SoC Physical Design with proven success across multiple tapeouts.
• Deep expertise in Floorplanning, Power Delivery Networks, Placement, CTS, Routing, Timing Closure, Signal Integrity, IR/EM Analysis, and Physical Verification.
• Strong understanding of advanced signoff methodologies including STA, SI, Power Integrity, Reliability, DRC/LVS, ERC, PERC, and ESD verification.
• Extensive experience with industry-standard EDA tools such as Innovus, ICC2/Fusion Compiler, PrimeTime, Tempus, Calibre, RedHawk, Voltus, and related signoff tools.
• Proven experience leading physical design execution on advanced technology nodes (5nm, 3nm, or equivalent).
• Strong expertise in low-power design methodologies, power-aware implementation, and multi-voltage designs.
• Demonstrated ability to drive technical decisions, solve complex design challenges, and influence cross-functional teams.
• Excellent leadership, communication, and stakeholder management skills.

Nice to have

• Experience in high-performance CPU, GPU, AI/ML, Mobile, Networking, Datacenter, or Multimedia SoCs.
• Demonstrated ownership of full-chip physical design and successful delivery of complex SoCs to production.
• Experience driving methodology development, flow automation, and design productivity improvements.
• Prior experience leading and mentoring teams of Physical Design engineers.
• Candidates from leading semiconductor product companies are strongly preferred.

Details

• Location: Bangalore, India.