SoC Physical Design Engineer

Overview

Physical design engineering role within Qualcomm's ASICS Engineering group, focused on SoC physical design, place and route, and sign-off for complex subsystems.

What you'll need

• Bachelor's degree in Electrical Engineering with 8 to 15 years of experience in physical design
• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience, OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience, OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience
• Experience managing complex subsystem and small teams
• Experience in synthesis, PnR, sign-off convergence, including Static Timing Analysis (STA) and sign-off optimizations
• Experience with demanding PPA requirements of complex subsystem/SoC, place and route, IP integration
• Experience in low power design implementation including UPF, multi-voltage domains, power gating
• Experience with ASIC design flows and methodology of physical design
• Understanding of circuit design, device physics and deep sub-micron technology
• Experience working on multiple tape-outs in advanced technology nodes

Nice to have

• Good understanding of automation to drive efforts to improve PPA

Details

• Location: Bangalore, India