Staff/Senior Staff Physical Design Engineer (Technical Lead)

Overview

Staff/Senior Staff Physical Design Engineer (Technical Lead) to lead physical design efforts for next-generation silicon products, using a player-coach approach to deliver critical sub-chip blocks and drive tape-out success.

What you'll do

• Lead a small team of physical design (PD) engineers with technical direction, workload management, and architectural oversight.
• Own the physical delivery of a major sub-chip or complex block, focusing on high-congestion and timing-critical areas.
• Act as primary architect for PD convergence and implement custom PPA recipes beyond standard vendor flows.
• Drive advanced automation by building Tcl and Python scripts for flow automation, data mining, and sign-off verification.
• Manage stakeholders across RTL, DFT, and synthesis, communicating risks and pushing left-shift optimizations.
• Ensure sign-off accountability including STA, EM/IR (Voltus/Apache), and physical verification (Pegasus/Calibre).

What you'll need

• Staff experience: 8–10 years; Senior Staff experience: 11–13 years.
• Expert-level proficiency in Cadence Innovus/Tempus for timing convergence.
• Deep expertise in static timing analysis (STA) for complex clocking, multi-corner sign-off, and crosstalk closure.
• Demonstrated ability to optimize PPA for advanced nodes (7nm, 5nm, or below) via custom floorplanning and CTS strategies.
• Advanced scripting proficiency in Tcl and Python for scalable, repeatable methodologies.
• Experience with multiple successful lead-level tape-outs.

Details

• Location: Bangalore or Remote in India (hybrid/remote available).