STA/Timing and Physical Design Engineer (Senior/Lead) - Modem Team

Overview

Seeking a Senior/Lead STA/Timing Engineer for advanced Modem SoCs within the Modem team, responsible for timing analysis and timing closure to achieve timing signoff.

What you'll do

• Perform block/full Modem STA and timing closure across MMMC scenarios.
• Drive setup/hold closure, ECO implementation, and timing signoff.
• Analyze timing from each Netlist to GDS stage.
• Collaborate with RTL, Physical Design (PD), and DFT teams to resolve timing issues.
• Analyze noise, crosstalk, and OCV/AOCV impacts and optimize critical paths.
• Validate timing constraints (SDC) and automate timing flows using Tcl/Perl/Python scripts.

What you'll need

• Minimum 6+ years (or 5+ years with a Master’s, or 4+ years with a PhD) in hardware engineering or related work.
• Bachelor’s/Master’s/PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
• Strong hands-on experience in STA, timing closure, MMMC, SDC, and ECO.
• Experience with Synopsys PrimeTime (PT/PrimeTime PTPX) and Cadence Tempus.
• Good understanding of digital design, synthesis, physical design, CTS, and routing.
• Scripting skills in Tcl/Perl/Python.

Details

• Location: Bangalore, India.