PDK Engineer

Overview

PDK Engineer (DRC Runset Engineer) to develop, validate, support, and optimize Design Rule Checking runsets for advanced semiconductor process nodes.

What you'll do

• Develop, maintain, and support DRC runsets/rule decks for advanced semiconductor process nodes.
• Translate process design rules into physical verification checks.
• Develop and validate geometric, connectivity, density, and process-specific DRC checks using Calibre, ICV, and Pegasus.
• Create test cases to validate rule deck functionality, coverage, and correctness.
• Debug DRC rule deck issues and resolve user-reported problems.
• Improve runset quality, runtime efficiency, scalability, and usability.
• Use AI-based tools and automation techniques to enhance rule deck development, validation, and debug productivity.

What you'll need

• 4+ years of experience with a Bachelor's degree or 2+ years with a Master's degree in Electronics/VLSI/Computer Engineering or related field.
• Experience developing DRC rule decks/runsets for semiconductor technologies.
• Hands-on expertise with one or more physical verification tools: Siemens Calibre, Synopsys ICV, Cadence Pegasus.
• Good understanding of semiconductor manufacturing process, layout design rules, and physical verification concepts.
• Experience writing, debugging, and optimizing DRC checks.
• Hands-on experience with layout and debug tools: Cadence Virtuoso, Calibre DRV, IC WorkBench.
• Programming/scripting skills in Python, Perl, Tcl, or Shell scripting.
• Ability to create and maintain validation test cases and regression suites.
• Strong debugging, analytical, and problem-solving skills.

Details

• Employment type: Experienced Hire.
• Shift: Shift 1 (India).
• Work model: On-site presence required.
• Primary location: India, Bangalore.