Overview
Drive synthesis and timing closure for NPU IPs and subsystems supporting high-performance AI/ML accelerators and next-generation SoCs.
What you'll do
- Own RTL-to-gate synthesis and timing closure for NPU designs.
- Develop synthesis flows, constraints, and automation for hierarchical designs.
- Drive pre-layout and post-layout timing closure across modes and process corners.
- Optimize performance, power, and area using physical-aware synthesis.
- Create and maintain SDC, clock, false-path, and multi-cycle-path constraints.
- Collaborate with RTL, DFT, STA, and Physical Design teams to resolve implementation issues.
- Support quality checks, tapeout activities, and synthesis methodology improvements.
What you'll need
- 3+ years of Hardware Engineering experience with a bachelor's degree, 2+ years with a master's degree, or 1+ year with a PhD.
- Bachelor's or master's degree in Electrical Engineering, Electronics, Computer Engineering, or a related field.
- Hands-on experience with RTL synthesis, timing closure, and constraint development.
- Expertise with Synopsys Design Compiler/Fusion Compiler or Cadence Genus.
- Strong timing analysis knowledge using PrimeTime.
- Experience with low-power methodologies, UPF flows, clocking architecture, and timing signoff.
- Proficiency in TCL and Python or Perl scripting.
Nice to have
- Experience with AI/ML accelerators, NPU, DSP, GPU, CPU, or high-performance compute architectures.
- Knowledge of 5nm, 4nm, 3nm, or smaller technology nodes.
- Experience with physical-aware synthesis and hierarchical design methodologies.
- Familiarity with LEC, CDC, lint, power analysis, and low-power verification flows.
- Successful SoC or IP tapeout experience.
Details
- Locations: Bangalore, India; Hyderabad, Telangana, India.
Read the full description and apply on the company’s own careers page.
