Staff Engineer - DFT

Overview

Staff Engineer on the Connectivity BU DFT and Timing team, working on DFT and STA for networking copper and optical products across the full SoC design flow.

What you'll do

• Develop timing constraints and set up timing modes and technology library infrastructure.
• Define DFT architecture and testability strategy, and define the timing and DFT flows.
• Implement and verify DFT/STA, including post-silicon bring-up.
• Implement, integrate and verify DFT features in the SoC with other DFT/STA team members.
• Interact closely with logic design, physical design, STA and ATE teams as needed.

What you'll need

• Bachelor's degree in Computer Science, Electrical Engineering or related fields and 6 years of related professional experience in DFT, or Master's and/or PhD in Computer Science, Electrical Engineering or related fields with 4 years of experience.
• Very good knowledge of SCAN, ATPG, JTAG and MBIST.
• Good knowledge of running tile-level and chip-level STA flows.
• Experience with one or more chip tapeouts that included full timing closure responsibility.
• Proven experience with gate-level simulations using no-timing and SDF-based simulations for DFT modes.
• Proven experience with DFT test structures, IP integration, ATPG fault models, test point insertion and coverage improvement techniques.
• Proven experience with scan insertion at block level and chip top level.
• Good knowledge of test mode timing constraints.
• Cross-domain knowledge to resolve DFT issues with design, synthesis, physical design and STA teams.
• Proficiency in industry-standard tools for scan insertion, ATPG, MBIST and JTAG.
• Good knowledge and understanding of JTAG under IEEE 1149.1/1149.6 standards.
• Experience with post-silicon ramp-up and debug on ATE.
• Good hands-on experience with memory BIST generation, insertion and verification at RTL and netlist level.
• Good knowledge of Perl and Tcl scripting.
• Very good team player capabilities and excellent communication skills to work across a global organization.
• High sense of responsibility and ownership for successful tapeout and post-silicon ramp-up.

Nice to have

• Preferably experience with Synopsys or Mentor tools.

Details

• Location: Bangalore.
• Eligible for Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers.
• Applicants must be eligible to access export-controlled information under applicable law; some applicants may be subject to an export license review prior to employment.