DFT Design Engineer

Overview

DFT Design Engineer role focused on scan/DFT implementation and verification, including ATPG and fault model expertise.

What you'll do

• Implement JTAG and memory BIST/repair circuitry (BIRA/BISR) using industry standard tools.
• Perform DFT verification using gate-level simulations with timing annotations.
• Troubleshoot DFT issues including simulation failures, ATPG coverage improvements, and DRC debug.
• Analyze timing constraints and perform DFT mode timing analysis.
• Work with post-silicon/manufacturing teams to debug and resolve ATE issues.
• Use RTL coding and shell scripting to support DFT development.

What you'll need

• Strong knowledge and experience in Spyglass DFT.
• Experience with Scan Architecture (SSN Topology) and ATPG with various fault models.
• 2+ years of DFT experience.
• B.E/B.Tech/M.E/M.Tech in Electrical/Electronics/Communication Engineering.

Details

• Location: India, Bangalore.
• Employment type: Intel Contract Employee.
• Shift: Shift 1.
• Work model: Hybrid (split time on-site at the assigned Intel site and off-site).