Engineer II - CAD

Overview

Engineer II in the CAD group at Microchip Technology, providing global EDA tool and design-flow support and developing next-generation ASIC design flows and methodology.

What you'll do

• Participate in various aspects of EDA support for the design community.
• Develop next-generation ASIC design flow and methodology.
• Work closely with business units across the globe to understand their needs and foster innovative ideas to solve complex problems.
• Design, benchmark, and deploy automated CAD tool flows focusing on logic synthesis, hierarchical optimization, physical synthesis, and chip sign-off timing.
• Write and optimize robust, scalable scripts using Tcl and Python to reduce Flow Turnaround Time (TAT) and build automated tracking tools for timing data.
• Build and optimize front-end flows utilizing advanced tools for logical/physical synthesis and Formal Verification/Logic Equivalence Checking (LEC).
• Standardize and automate the validation of Synopsys Design Constraints (SDC) across all functional and test modes.
• Partner directly with major EDA vendors to test next-generation features, troubleshoot internal tool failures, and adapt flows for deep sub-micron advanced process nodes.

What you'll need

• Good knowledge of design flows from RTL design through synthesis, formal verification, and timing closure for RTL2GDS delivery.
• Hands-on experience with one or more of the following industry-standard toolsets: Synopsys Fusion Compiler, DC, PrimeTime; Cadence Genus, Tempus or Innovus.
• Excellent verbal and written communication skills.
• B.E./B.TECH/M.E./M TECH (Electronics/ECE/CS/VLSI).
• 2 to 8 years of relevant experience is required.

Nice to have

• Exposure to leveraging AI driven EDA capabilities (e.g., Synopsys FC.ai, Cadence Cerebrus) to automate PPA exploration and timing closure optimization.

Details

• Location: Bangalore, India.
• Travel: 0% - 25%.