Design Engineer II

Overview

Design Engineer II role focused on foundry PDK design enablement and technology/process-to-design bridging for advanced semiconductor technology.

What you'll do

• Validate, deploy, and maintain foundational PDK components for advanced technology nodes.
• Benchmark standard cells, SRAM, and custom circuits and optimize interconnects for PPA.
• Design and maintain scripts and automated execution flows for PDK enablement/validation and analysis.
• Partner with internal DTCO groups to convert device architectures into reality.

What you'll need

• 2–4 years of hands-on experience in semiconductor technology analysis and foundry PDK enablement.
• Experience with co-optimization of PDK components including LVS, DRC, parasitic extraction, and spice models.
• Strong understanding of CMOS device physics including GAA, FinFETs, and planar MOSFETs.
• Deep knowledge of LVS, DRC, parasitic extractions, and transistor-level spice models.
• Strong understanding of PDK design enablement flows.
• Proven experience interfacing with core PDK development and technology benchmarking groups.

Details

• Location: BANGALORE.