GPU (RTL) Design - Sr Lead

Overview

Senior Lead role for ASIC RTL Design focused on RTL coding, multi-clock domain integration, and verification/debug collaboration.

What you'll do

• Design and integrate complex multi clock domain blocks.
• Develop RTL using Verilog/System-Verilog.
• Work with clocking/reset/debug architecture for multi-clock/async interfaces.
• Collaborate with design verification and validation teams for pre/post-silicon debug.
• Apply ASIC development tool workflows including lint, CDC, Design Compiler, and Primetime.
• Support timing concepts needed for ASIC synthesis.

What you'll need

• Minimum 4 to 8 years of work experience in ASIC RTL Design.
• Logic design, micro-architecture, and RTL coding experience is required.
• Hands-on Verilog/System-Verilog experience is required.
• Knowledge of AMBA protocols including AXI, AHB, and APB is required.
• Hands-on experience with multi-clock designs and asynchronous interfaces is required.
• Tool experience with Lint, CDC, Design compiler, and Primetime is required.
• Experience/synthesis understanding of timing concepts for ASIC is required.

Details

• Location: Bangalore, India.