Design Engineer

Overview

Altera is seeking a highly motivated Design Engineer to contribute to the development of cutting-edge FPGA and SoC solutions, involved in the full design lifecycle from concept to silicon.

What you'll do

• Perform RTL design, verification, and synthesis of complex digital circuits for FPGA and SoC products.
• Develop and execute comprehensive test plans and verification environments using industry-standard methodologies.
• Collaborate with architecture, validation, and software teams to define specifications and ensure design integrity.
• Analyze and debug design issues, performing root cause analysis and implementing effective solutions.
• Optimize designs for performance, power, and area targets.
• Participate in design reviews and contribute to continuous improvement of design methodologies and processes.
• Generate design documentation, including specifications, test plans, and release notes.
• Hardware power-on and debug.
• New product release and rollout support.
• Customer technical support.

What you'll need

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• 3+ years of experience in digital IC design, with a focus on RTL design and verification.
• Proficiency in Verilog or SystemVerilog for RTL design and testbench development.
• Experience with industry-standard EDA tools for simulation, synthesis, and static timing analysis.
• Strong understanding of digital design fundamentals, including clock domain crossing (CDC) and reset synchronization.
• Familiarity with scripting languages such as Python or Perl.
• Excellent problem-solving, analytical, and debugging skills.
• Strong communication and interpersonal skills, with the ability to work effectively in a team environment.

Nice to have

• Preferred to have system level understanding.
• Proficiency with System Verilog and RTL coding skills, timing closure, or STA, targeting high performance designs.
• Very good understanding of latest protocol specifications for memory, bus protocol specification like AXI, PCIe and Ethernet interfaces, Security IPs (for ex: MACSec).
• Experience with FPGA tools and timing closure.
• Prior experience with FPGA architectures and design flows.

Details

• Location: Bengaluru, Karnataka, India.
• Job type: Regular.
• Shift: Shift 1 (India).