Chassis IP Design Engineer

Overview

Chassis IP Design Engineer role on Intel's UIC Fabric Design team within the Central Engineering Group, developing RTL logic for reusable IP blocks and subsystems that feed Intel's SoC solutions.

What you'll do

• Design and develop RTL code for IP blocks, ensuring functionality, quality, and scalability.
• Optimize logic designs to meet power, performance, area, and timing objectives.
• Collaborate with architecture teams to define microarchitecture features of IP designs.
• Participate in verification plan reviews and implement corrective measures for failing RTL tests.
• Support SoC integration teams to ensure high-quality integration and verification of IP blocks.
• Work with physical design teams to address timing and implementation challenges.
• Drive compliance with quality assurance standards for seamless IP-SoC handoff.

What you'll need

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field with 4+ years of experience in state-of-the-art SoC or IP design, or Master's degree with 3+ years of experience.
• Proficiency in Verilog/System Verilog, including Lint/CDC/RDC tools and methodologies.
• Demonstrated ability to optimize designs for power, performance, and area trade-offs (PPA).

Nice to have

• Familiarity with AMBA (CHI, AXI, AHB, APB) and PCIe/CXL protocols.
• Experience in designing IP subsystems, including protocol conversion bridges and debug/trace components.
• Understanding of concepts such as QoS, access control, flow control, RAS, and security/error handling.
• Proven ability to collaborate across architecture, verification, and SoC integration teams effectively.
• Familiarity with using AI tools to assist logic design.
• Strong communication skills and experience working with globally distributed teams across time zones.

Details

• Location: Bangalore, India.
• Shift: Shift 1 (India).
• Work model: Hybrid, splitting time between on-site at the assigned Intel site and off-site.
• Employment type: Experienced Hire.