Senior ASIC Design Engineer - XBAR IP

Overview

Senior ASIC design engineer on NVIDIA's Graphics team, working on memory subsystem components used in its graphics processors. The role covers micro-architecture and RTL development through to a fully verified, synthesis- and timing-clean design.

What you'll do

• Own micro-architecture and RTL development of design modules.
• Micro-architect features to meet performance, power and area requirements.
• Work with HW architects to define critical features.
• Collaborate with verification teams to verify the correctness of implemented features.
• Cooperate with timing, VLSI and physical design teams to ensure the design meets timing and interface requirements and is routable.
• Interact with FPGA and S/W teams to prototype the design and ensure that S/W is tested.
• Work on post-silicon verification and debug.

What you'll need

• BS / MS or equivalent experience.
• 5+ years of design experience.
• Experience in RTL design of complex design units for at least two or three projects.
• Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).
• Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up and lab debug.
• Expertise in Verilog.

Nice to have

• Design experience in memory subsystem or network interconnect IP.
• Good debugging and problem solving skills.
• Scripting knowledge (Python/Perl/shell).
• Leadership experience in leading small 2-3 member teams.
• Good interpersonal skills and ability and desire to work as part of a team.

Details

• Location: India, Bengaluru.
• Work mode: Hybrid (#LI-Hybrid).