Senior ASIC Design Engineer, GPU Core Pipeline IP

Overview

Senior ASIC Design Engineer on the ASIC Design team, contributing to the design and implementation of graphics and compute features within a GPU IP.

What you'll do

• Contribute to the design and implementation of graphics and compute features within an IP.
• Be responsible for the micro-architecture and RTL design of GPU ASICs.
• Develop RTL using Verilog/SystemVerilog.
• Collaborate on design specifications.
• Ensure designs meet performance, power, area, and timing goals.
• Work with HW architects and designers to make the right implementation choices.
• Collaborate with verification engineers to ensure comprehensive validation and coverage of all implemented functionality.
• Participate in silicon bring-up, post-silicon debug, and performance analysis as needed.

What you'll need

• B.Tech./ M.Tech. with 5+ years of relevant experience.
• Familiarity with Verilog, C++ and OOPs concepts.
• Experience in RTL design and micro-architecture development at the unit or subsystem level.
• Good understanding of digital design fundamentals, including synchronous design, timing, and clock/reset methodologies.
• Good understanding of computer architecture concepts.
• Strong technical fundamentals with superior analytical and problem-solving skills.

Nice to have

• Knowledge of SystemVerilog and ASIC design methodologies.
• Exposure to industry-standard design, simulation, and debug tools.
• Prior experience in 3D graphics processing or processor design.
• C/C++ programming language experience.
• Experience in scripting and tool development using Perl and Python.
• Excellent debugging skills.
• Understanding of ASIC implementation flows including synthesis, timing closure, DFT, and physical design considerations.
• Good interpersonal & communication skills.

Details

• Location: Bengaluru, India.
• Work mode: Hybrid.