CPU Senior Floor Plan Engineer

Overview

Defines the physical dimensions of the CPU IP, including floorplanning, pin placement and die size estimation, working with architecture, DFT, package and physical design teams to arrive at an optimal chip plan early in the design cycle.

What you'll do

• Define the physical dimensions of the CPU IP, considering die size optimization, good die per wafer maximization, technology selection and metal layer reuse across SKUs.
• Perform integration of all dies in a package and complete the relevant checks before tape out.
• Create the physical database for the IP.
• Collaborate with architects to optimize IP placement for latency and die area/aspect ratio.
• Create specifications and collaterals for IP blocks to execute floorplan and automatic place and route (APR) at subsequent hierarchies.
• Collaborate with clock design and logic design teams to deliver physical block level floorplans for APR.
• Collaborate with the power delivery team on tradeoffs for metal allocation between signal and power.
• Be responsible for all aspects of floorplan and pin placement activities.
• Engage with architecture, DFT and package teams to arrive at optimal chip planning early in the design cycle.
• Work closely with physical design cluster leads to understand design challenges and arrive at an optimal floorplan.
• Play a critical role in die size estimation and in evaluating floorplan tools, methods and flows.
• Plan boundaries and pin densities to facilitate high confidence timing closure and routability.
• Identify and solve design issues at partition/cluster and full chip level.

What you'll need

• Bachelor's degree in a relevant field such as Electrical Engineering, Electronics Engineering, or equivalent education, with 3+ years of hands-on experience OR Master's degree in a relevant field with 2+ years of hands-on experience.
• Proven expertise in floorplanning, APR flows, and physical design verification flows using Synopsys or Cadence tools.
• Proficiency in hierarchical design approach, top-down design, budgeting, timing and physical convergence.
• Strong knowledge of submicron process nodes and layout verification methodologies such as LVS and DRC.
• Experience handling IP/partition/block with multiple voltage and clock domains, ESD strategies, mixed signal block integration, and advanced package technologies.
• Expertise with multiple aspects of ASIC integration including floorplanning, clock and power distribution, global signal planning, I/O planning and hard IP integration.

Nice to have

• Familiarity with scripting languages such as Tcl, Perl, or Python for automation in physical design workflows.
• Effective communication skills for collaboration across multidisciplinary teams.
• Proven ability to work in dynamic and cross-geographical environments.
• Knowledge of feature feasibility studies and advanced design flow methodologies.

Details

• Location: India, Bangalore.
• Work model: hybrid, splitting time between on-site at the assigned Intel site and off-site.
• Shift: Shift 1 (India).
• Job type: Experienced Hire.