Senior CAD Engineer - Floor Plan

Overview

Senior CAD Engineer supporting Design Planning and RTL-to-Floorplan methodology for next-generation CPU IP development, working closely with CPU Physical Design, Architecture, RTL and CAD teams.

What you'll do

• Own and support Design Planning and RTL to Floorplan methodology deployment across CPU IP programs.
• Develop, maintain and enhance automation frameworks for RTL to Floorplan, Design Planning, physical-aware RTL analysis, floorplan generation flows, PPA estimation, and early congestion and routability analysis.
• Provide technical support to Physical Design teams by debugging flow, tool and methodology issues.
• Drive continuous improvements in Design Planning flow quality, robustness, scalability and usability.
• Develop automation solutions to improve engineering productivity and reduce manual effort.
• Create dashboards, reporting infrastructure and analytics frameworks to track methodology health, usage and quality metrics.
• Work closely with implementation teams to identify workflow bottlenecks and deploy automation-based solutions.
• Support the adoption and deployment of new EDA tool capabilities, releases and methodology enhancements.
• Enable methodology correlation and consistency across CPU IP projects and technology nodes.
• Partner with internal CAD organizations and EDA vendors to evaluate and integrate new Design Planning capabilities.
• Drive best practices, documentation, training materials and user support for Design Planning methodologies.
• Explore Machine Learning, Generative AI and Agentic AI solutions to improve methodology deployment, flow debugging and productivity.

What you'll need

• M.Tech/MS in Electrical Engineering, Computer Engineering, Computer Science, VLSI, or a related field.
• 4+ years of industry experience in CAD Engineering, Design Automation, Physical Design Methodology, EDA Tool Development or Physical Design Infrastructure.
• Strong understanding of Physical Design flows, RTL-to-Floorplan methodologies, Design Planning concepts, floorplanning fundamentals, and PPA analysis and optimization.
• Experience supporting and deploying implementation tools such as Synopsys Fusion Compiler, ICC2, Cadence Innovus, or equivalent physical implementation platforms.
• Strong software development and scripting skills in Python, Tcl and Shell scripting.
• Experience building and maintaining production-quality CAD automation and methodology frameworks.

Nice to have

• Experience supporting CPU Core, Cache, Fabric, or other high-performance IP development teams.
• Experience developing methodologies and automation for RTL-FP Design Planning, physical-aware design, design quality assessment and early PPA estimation.
• Experience with advanced technology nodes such as Intel 18A/14A, TSMC N3/N2, or equivalent.
• Experience with distributed compute infrastructure, cloud-based design environments and large-scale CAD systems.
• Familiarity with Machine Learning, Data Analytics, LLMs and Agentic AI frameworks for EDA applications.
• Working knowledge of timing, power, congestion, routability and signoff considerations impacting design planning methodologies.

Details

• Location: India, Bangalore.
• Work model: Hybrid, splitting time between on-site work at the assigned Intel site and off-site.
• Shift: Shift 1 (India).
• Job type: Experienced Hire.