NPU/AI Processor Synthesis (Design implementation) - Staff Engineer

Overview

Staff Engineer responsible for RTL-to-GDS synthesis and timing closure for NPU design teams developing high-performance AI/ML accelerators.

What you'll do

• Own RTL-to-gate synthesis and timing closure for NPU IPs and subsystems.
• Develop synthesis flows, constraints, and automation for hierarchical designs.
• Drive pre-layout and post-layout timing closure across modes and process corners.
• Optimize performance, power, and area using physical-aware synthesis.
• Create and maintain SDC, clock, false-path, and multi-cycle-path constraints.
• Resolve QoR, timing, power, and convergence issues with cross-functional teams.
• Support quality checks, tapeout activities, and synthesis methodology improvements.

What you'll need

• 4+ years of Hardware Engineering or related experience with a bachelor's degree, 3+ with a master's, or 2+ with a PhD.
• Bachelor's or master's degree in Electrical Engineering, Electronics, Computer Engineering, or a related field.
• Strong understanding of ASIC design flow from RTL to GDS.
• Hands-on RTL synthesis, timing closure, and constraint-development experience.
• Expertise with Synopsys Design Compiler/Fusion Compiler or Cadence Genus.
• PrimeTime timing analysis and low-power UPF flow experience.
• Proficiency in TCL and Python or Perl scripting.

Nice to have

• Experience with AI/ML accelerators, NPU, DSP, GPU, CPU, or other high-performance architectures.
• Knowledge of 5nm, 4nm, 3nm, or smaller technology nodes.
• Physical-aware synthesis, hierarchical design, verification-flow, or SoC/IP tapeout experience.

Details

• Staff Engineer experience range: 8–12 years.
• Locations: Bangalore and Hyderabad, India.