Physical Design Automation Engineer

Overview

Technical Lead for APR Design Automation in Intel Foundry India's Design Technology Platform team, developing and optimizing RTL-to-GDS flows primarily on Cadence Innovus, and supporting test chip and foundry IP needs on Intel's latest process nodes.

What you'll do

• Lead the development, deployment, and continuous improvement of RTL-to-GDS flows using Cadence Innovus as the primary PnR platform.
• Define and drive physical design tools, flows, and methodologies, including block-level implementation and integration, floorplanning, placement, CTS, and routing automation, and timing closure methodologies.
• Develop and maintain Tcl-based scripting and automation to enhance layout productivity within Innovus and related Cadence tools.
• Evaluate and benchmark Cadence Innovus vs. Synopsys Fusion Compiler flows and provide data-driven recommendations on tool and methodology selection.
• Enable and support industry-standard static timing analysis (STA) tools for test chips and Foundry IPs (FIPs), and ensure continued support and enhancement.
• Collaborate with central CAD, design teams, local CAD teams, and EDA vendors (Cadence, Synopsys) to define next-generation PnR methodologies.
• Work closely with internal and external design customers to understand requirements and deliver robust, scalable automation solutions.
• Respond to customer and client requests proactively, developing solutions leveraging formal expertise and engineering judgment.
• Contribute to process node bring-up by validating and refining flows on Intel's latest technology nodes.

What you'll need

• Master's degree in M.Tech or MS in Microelectronics, Electronics Engineering, or an equivalent qualification from a reputed institute, with relevant industry experience in physical design and APR flow development.
• Proven hands-on experience in block-level design closure using Cadence Innovus Implementation System as the primary APR tool for end-to-end RTL-to-GDS flows.
• Strong working knowledge of floorplanning (die size estimation, macro placement and pin assignment), power planning (power grid design, IR drop awareness, ring and stripe strategies), placement (timing-driven and congestion-aware), clock tree synthesis (clock tree design, skew and latency optimization), and routing (global and detailed routing, DRC-clean routing closure).
• Well-versed with multiple Cadence Innovus optimization techniques for design closure, including timing, area, power, and congestion optimizations.
• Ability to guide and mentor the team in resolving complex implementation challenges and providing structured solutions.
• Strong understanding of digital timing concepts including setup, hold, clock domain crossing (CDC), and multi-mode multi-corner (MMMC) analysis.
• Ability to analyze and validate design constraints (SDC) and understand their impact on timing closure.
• Experience with industry-standard STA tools such as Cadence Tempus or equivalent for timing sign-off.
• Demonstrated experience in achieving full layout closure for blocks, ensuring compliance with DRC, LVS, density requirements and antenna violation fixes.
• Familiarity with physical verification tools and sign-off flows as per process technology specifications.
• Good understanding of top-level integration challenges and ability to ensure block-level deliverables meet project-level timing and layout requirements.
• Experience in managing block-to-top handoffs and resolving integration-level issues effectively.
• Strong foundation in VLSI design, digital electronics, and semiconductor device fundamentals.
• Good understanding of digital design timing closure principles and methodologies.
• Strong analytical and problem-solving skills with a structured approach to debugging complex physical design issues.
• Proactive and transparent communication style, with the ability to articulate technical challenges and solutions clearly to stakeholders.
• Collaborative mindset and ability to work effectively in a diverse, cross-functional, and geographically distributed team.
• Ability to work across multiple domains including design, CAD, and EDA vendor teams.

Nice to have

• Working knowledge of Synopsys Fusion Compiler.
• Knowledge of semiconductor fabrication and process technology.
• Familiarity with Intel process technology or advanced node design environments.
• Leadership experience in driving block-level closure and physical design sign-off for tape-out.
• Demonstrated track record of silicon success, having contributed to or led designs that have been taped out and validated in silicon.

Details

• Experienced hire, Shift 1 (India).
• Location: Bangalore, India.
• On-site work model.