Principal Physical Design Engineer

Overview

Physical design role supporting complex SoC/silicon products for Server, Storage, and/or Networking applications at Astera Labs.

What you'll do

• Own full chip or block level physical design from architecture to GDSII, driving multiple complex designs to production.
• Perform synthesis, timing closure and formal verification (equivalence) at the block and full-chip level.
• Work with IP vendors for both RTL and hard-mac blocks.
• Plan and prepare for customer meetings in advance and prioritize a dynamic list of multiple tasks with minimal guidance and supervision.

What you'll need

• Strong academic and technical background in electrical engineering.
• A Bachelor's degree in EE / Computer is required.
• 10+ years' experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Hands-on and thorough knowledge of synthesis, place and route, CTS, extraction timing analysis/STA, Physical Verification and other backend tools and methodologies for technologies 16nm or less, preferably 7nm or less.
• Proven expertise in synthesis, timing closure and formal verification (equivalence) at the block and full-chip level.
• Full chip or block level ownership from architecture to GDSII, driving multiple complex designs to production.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity and working knowledge of System Verilog/Verilog.
• Experience with DFT tools and techniques.
• Experience in working with IP vendors for both RTL and hard-mac blocks.
• Good scripting skills in Python or Perl.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude; think and act fast with the customer in mind.

Nice to have

• A Master's degree in EE / Computer.
• Good knowledge of design for test (DFT), stuck-at and transition scan test insertion.
• Familiarity with DFT test coverage and debug.
• Familiarity with ECO methodologies and tools.

Details

• Location: Bengaluru, Karnataka, India.