Physical Design Engineer

Overview

Physical design engineer applying and leading Broadcom's design methodology and milestone flow to achieve right-first-time silicon, with a focus on block- and top-level layout.

What you'll do

• Understand SoC top-down and bottom-up physical design integration in 5nm and lower technologies.
• Apply deep functional knowledge of P&R flows and adapt quickly to internal flows.
• Implement timing and functional ECO.
• Execute P&R, extraction and physical verification, working towards STA closure.
• Build automation flows where needed, or adapt existing flows for re-use.
• Lead by example and bring tangible improvement in TAT with better quality.

What you'll need

• MSEE/MSCS with 10+ years of experience, or BSEE/BSCS with 12+ years of experience.
• Very good experience in block- and level-layout activities, including floor-planning, partitioning, placement, clock tree synthesis, route and physical verification.
• A deep understanding of the backend digital design flow.
• Proficient in timing constraints and physical constraints.
• Proficient in handling EDA tools across floorplan, partition, placement, CTS and route stages for SoC top.
• Proficient with backend EDA tools such as Genus, Innovus, Quantus, Tempus, DC, Star-RCXT, PT, PrimeRail, Voltus and Redhawk.
• Proficient in any of the Cadence, Synopsys or Mentor EDA tools for P&R, PV, STA and ECO.
• Proficiency in Tcl and Perl.
• High expertise in one industry programming language for automation.
• Excellent analytical skills.
• Ability to collaborate in a multi-functional environment, cross-site or cross-time zone.

Details

• Location: Pune, India (EON Kharadi Infrastructure).