Principal Physical Design Engineer

Overview

Principal Physical Design Engineer role at Astera Labs, responsible for backend physical design of complex SoC/silicon products for Server, Storage, and/or Networking applications.

What you'll need

• Bachelor's degree in EE / Computer is required
• ≥8 years' experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications
• Strong academic and technical background in electrical engineering
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision
• Entrepreneurial, open-minded behavior and can-do attitude; think and act fast with the customer in mind
• Hands-on and thorough knowledge of synthesis, place and route, CTS, extraction timing analysis/STA, Physical Verification and other backend tools and methodologies for technologies 16nm or less, preferably 7nm or less
• Proven expertise in synthesis, timing closure and formal verification (equivalence) at the block and full-chip level
• Full chip or block level ownership from architecture to GDSII, driving multiple complex designs to production
• Experience with Cadence and/or Synopsys physical design tools/flows
• Familiarity and working knowledge of System Verilog/Verilog
• Experience with DFT tools and techniques
• Experience in working with IP vendors for both RTL and hard-mac blocks
• Good scripting skills in Python or Perl

Nice to have

• Master's degree
• Good knowledge of design for test (DFT), stuck-at and transition scan test insertion
• Familiarity with DFT test coverage and debug
• Familiarity with ECO methodologies and tools