ASIC Engineer

Overview

Physical Design role on Cisco's SiliconOne team in Bangalore, India, working on next generation networking chips in advanced process nodes.

What you'll do

• Drive the backend process through the entire RTL to GDS implementation flow.
• Perform hierarchical floor planning, place and route, and timing closure.
• Carry out power integrity analysis, static timing verification, physical verification and equivalence checks.
• Focus on performance and die size optimization.
• Develop automation scripts within STA tools for methodology development.
• Drive methodologies and best known methods to streamline and automate physical design work.
• Develop timing ECO implementation strategy and convergence.
• Evaluate multiple timing methodologies and tools on different designs and technology nodes.

What you'll need

• Bachelor's or Master's degree in Electrical or Computer Engineering.
• 8+ years of experience.
• All aspects of ASIC physical implementation including floor planning, clock and power distribution, global signal planning, I/O planning and hard IP integration.
• Hierarchical design implementation approach, timing closure, physical convergence.
• Excellent debugging skills in implementation issues and ability to produce creative solutions.
• Power integrity analysis.
• STA setup, convergence methodology, reviews and sign-off for multi-mode and multi-corner designs.
• Experience with large designs (>100M gates) using state of the art sub 16/14/7/5/3nm technologies.

Nice to have

• Analyze current generation quality and efficiency gaps to identify incremental or evolutionary changes to existing physical design tools, flow and methodology.
• Good understanding of different CTS strategies and providing feedback to the implementation team.
• Experience enabling Tweaker/PrimeTime based ECO flows.

Details

• Location: Bangalore, India.