Tech Lead ASIC Design Engineer

Overview

Lead the design and implementation of complex digital IPs and SoC subsystems for next-generation AI infrastructure connectivity products, providing technical leadership and mentoring engineers.

What you'll do

• Lead the architecture, microarchitecture, RTL design, and implementation of complex digital IPs and SoC subsystems for high-performance connectivity products.
• Drive end-to-end ownership of design modules from specification through RTL development, integration, and silicon bring-up.
• Design high-quality, synthesizable RTL using Verilog/System Verilog, ensuring optimal performance, power, area (PPA), and scalability.
• Develop complex data paths, control logic, finite state machines, arbitration mechanisms, and protocol engines.
• Design and implement solutions for high-speed interfaces and protocols, including CXL, PCIe, Ethernet, and AXI-based interconnects.
• Collaborate with Architecture teams to define microarchitecture and review functional specifications.
• Partner closely with Design Verification teams to develop verification strategies, debug design issues, and achieve functional closure.
• Work with Physical Design teams to resolve timing, power, congestion, and implementation challenges through RTL optimization.
• Support synthesis, lint, CDC/RDC, STA, DFT, and design sign-off activities.
• Participate in design reviews and ensure compliance with RTL coding guidelines and design best practices.
• Drive debug and resolution of RTL, integration, and post-silicon issues in collaboration with firmware, validation, and system engineering teams.

What you'll need

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
• 6–12 years of experience in digital design for complex semiconductor products.
• Strong expertise in Verilog/System Verilog RTL design.
• Experience with complete ASIC design cycles from microarchitecture through RTL implementation and silicon bring-up.
• Strong understanding of digital design fundamentals, computer architecture, and SoC integration.
• Experience with synthesis, lint, CDC/RDC, STA, and RTL sign-off methodologies.
• Excellent debugging and analytical skills.

Nice to have

• Experience in one or more of the following: Compute Express Link (CXL); PCI Express (PCIe); Ethernet MAC/PCS; High-speed networking or connectivity IP; AXI-based SoC architecture; DMA engines; Packet processing pipelines; Cache coherency protocols; Memory controllers; High-speed interconnects.
• Tools and methodologies: Verilog/System Verilog; Synopsys Design Compiler; Cadence Genus; SpyGlass (Lint/CDC/RDC); Static Timing Analysis (STA); Git or other version control systems; Python, Tcl, Perl, or Shell scripting.
• Experience designing connectivity, networking, storage, or AI accelerator silicon.
• Proven track record of delivering successful ASIC or SoC tape-outs.
• Familiarity with high-speed protocols and data center technologies.
• Experience working in cross-functional global engineering teams.
• Exposure to low-power design methodologies and Design for Test (DFT).

Details

• Location: Bengaluru, India.
• Work mode: Hybrid.