ASIC Verification Engineer

Overview

Work onsite as an ASIC Verification Engineer, developing and executing verification solutions for complex ASICs using SystemVerilog, UVM, and industry-standard simulators.

What you'll do

• Develop and enhance ASIC verification environments using UVM.
• Build block-level, subsystem, and full-chip verification environments.
• Define and execute verification suites and test cases.
• Verify ASIC blocks and analyze coverage and gate-level simulation results.
• Debug design issues with logic designers.
• Support software teams during bring-up and validation.
• Develop Perl, Python, and/or Shell scripts for automation.

What you'll need

• 3+ years of experience in ASIC verification.
• Bachelor's or Master's degree in Electrical Engineering.
• Strong SystemVerilog experience for ASIC verification.
• Experience with constrained-random verification techniques.
• Hands-on experience with OVM, VMM, or UVM.
• Proficiency in Perl, Tcl, Python, or Shell scripting.
• Strong problem-solving, debugging, analytical, and collaboration skills.

Nice to have

• Experience verifying networking protocols such as Ethernet.

Details

• Work mode: Onsite.
• Location: Bengaluru, Karnataka, India.