CPU Hardware Verification (Power Management) Staff Engineer

Overview

Staff Engineer to lead end-to-end verification of CPU Co-Processor (CPUCP/PDP) power management firmware and hardware features.

What you'll do

• Own verification strategy from architecture definition through signoff for CPUCP/PDP power management.
• Architect and develop SystemVerilog/UVM testbenches, transactors, checkers, and verification infrastructure.
• Drive verification of AMBA-based system IPs (timers, mailbox, interrupts, NoC interconnect fabrics).
• Validate power-management features including DVFS, Low Power Modes (LPM), clock/power transitions, and firmware-controlled sequences.
• Lead complex debug and root-cause analysis across Firmware, RTL, Design, Emulation, and Post-Silicon teams.
• Develop reusable stimulus, automation, debug utilities, dashboards, and productivity tools for execution/scalability.

What you'll need

• SystemVerilog/UVM verification and testbench architecture experience.
• Experience validating power-management technologies such as DVFS and LPM.
• Deep understanding of AMBA protocols and system-level IPs (timers, mailboxes, interrupts, memory-mapped peripherals).
• Proficiency in C/C++, SystemVerilog, Python, and scripting/automation for data-driven verification workflows.
• Experience with RTL simulation, emulation, waveform analysis, debug methodologies, and coverage closure.
• Extensive experience in SoC, CPU, or power-management verification environments.

Details

• Location: Bangalore, India.