Turing-IP Design Verification - Sr Engineer

Overview

DV Engineer in Qualcomm’s IP verification team, responsible for functional verification of complex IPs and subsystems used in next-generation SoCs.

What you'll do

• Drive functional verification of IPs and subsystems from planning through sign-off.
• Create verification plans, testbench architecture, and test cases from design and architecture specs.
• Build reusable, scalable verification environments using SystemVerilog and UVM.
• Develop constrained-random and directed tests, assertions, and functional coverage models.
• Perform coverage closure and debug failures using waveform and log analysis.
• Collaborate with design, architecture, and SoC integration teams to resolve issues and ensure verification completeness.
• Handle regression setup, triage, and maintenance to support verification quality and throughput.

What you'll need

• 3 to 5 years of hands-on experience in ASIC/SoC functional verification.
• Strong proficiency in SystemVerilog and UVM methodology.
• Proven experience in IP, subsystem, and/or SoC-level verification.
• Knowledge of constrained-random stimulus, functional coverage, assertions (SVA), and scoreboarding.
• Debug experience using simulation logs and waveform tools (e.g., Verdi/FSDB).
• Understanding of digital design fundamentals, bus protocols, and SoC architecture.

Details

• Location: Bangalore, India.