Senior IP Design Verification Engineer - XBAR IP

Overview

Senior IP Design Verification Engineer to verify the design and implementation of next-generation memory subsystem units for GPUs and SoCs.

What you'll do

• Verify ASIC design, architecture, and micro-architecture of memory subsystems/units.
• Define verification scope and develop verification infrastructure.
• Create test plans, tests, and verification infrastructure for complex IPs.
• Build reusable bus functional models, monitors, checkers, and scoreboards using coverage-driven verification.
• Use advanced verification methodologies such as SV/UVM.
• Perform functional coverage-driven verification closure.
• Coordinate with architects, designers, and pre/post-silicon verification teams.

What you'll need

• Hold B.Tech./M.Tech. or equivalent experience.
• Have 4+ years of relevant experience.
• Verify complex IPs/units and sub-systems.
• Use random stimulus with functional coverage and assertion-based verification.
• Have expertise in Verilog.
• Know SystemVerilog or similar HVL/UVM/VMM.

Nice to have

• Experience verifying memory subsystem or network interconnect IP.
• Debugging and analytical skills with scripting knowledge.
• Good communication and team player.

Details

• Work mode: Hybrid (#LI-Hybrid).