Principal Engineer- Design Verification

Overview

Verification Lead for next-generation UA Link Switch products in the Memory Interface Division, driving verification strategy, architecture, execution, and first-silicon success.

What you'll do

• Define and own the verification strategy, methodology, and execution plan.
• Lead verification architecture, testbench development, coverage planning, and verification closure.
• Build scalable UVM/SystemVerilog verification environments for complex SoC and subsystem designs.
• Collaborate with cross-functional teams to ensure comprehensive verification coverage.
• Develop verification plans for functionality, performance, reliability, error handling, and corner cases.
• Drive debug and root-cause analysis of design and verification issues.
• Define and track verification metrics and lead verification reviews and sign-offs.

What you'll need

• 18+ years of experience in ASIC/SoC verification.
• Experience delivering complex SoC/subsystem verification programs from architecture through tape-out.
• Strong expertise in SystemVerilog, UVM, and Assertion-Based Verification (SVA).
• Knowledge of functional/code coverage methodologies and simulation/regression infrastructure.
• Experience verifying large-scale high-speed digital systems involving switching fabrics/interconnect and memory subsystems.
• Strong understanding of RTL design concepts and hardware architecture.
• Bachelor’s, Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, or related field.

Details

• Role located in the Memory Interface Division (MID).