RISCV Infra System IP DV - Sr Staff Engineer

Overview

Sr Staff Engineer for RISC-V IP system design verification in the hardware engineering area. You will plan, build, and execute verification activities for complex IP/subsystems and drive coverage closure and debug with related teams.

What you'll do

• Develop verification test plans and test cases to cover the design feature set.
• Create and run DV test benches using UVM and SystemVerilog and associated verification components.
• Monitor and drive code coverage and functional coverage closure across different test-bench levels.
• Collaborate with system architects, design, and emulation teams to debug failures and close coverage.
• Debug regression signatures, identify bug fixes, and track verification issues.
• Work with bus protocols including CHI/AHB/AXI/ACE/ACE-Lite and interconnect concepts.
• Apply knowledge of ARM/RISCV system architecture and related concepts for verification.

What you'll need

• Bachelor’s degree (or higher) in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
• 6+ years (bachelor’s) or 5+ years (master’s) or 4+ years (PhD) of hardware engineering or related work experience.
• Expertise in UVM and SystemVerilog DV test benches.
• Experience with verification collaterals such as checkers, trackers, scoreboards, assertions, and functional coverage.
• Experience with ARM/RISCV system architecture, including memory management/virtual memory concepts.
• Knowledge of multi-core ARMv8/v9 CPU architecture, coherency protocols, and virtualization.
• Communication skills to work with a large worldwide design organization.

Details

• Location: Bangalore, India.