ASIC Design Verification Engineer

Overview

Design and execute ASIC verification environments and test suites for complex chips, working primarily from an HPE office in Bengaluru.

What you'll do

• Develop and enhance ASIC verification environments using the latest methodologies such as UVM.
• Architect and build block-level, subsystem, and full-chip verification environments using SystemVerilog and UVM.
• Define, design, and execute verification suites and test cases for complex ASICs using front-end simulators such as VCS and NC.
• Independently verify large ASIC blocks and drive tape-out readiness through code coverage, functional coverage, and gate-level simulation analysis.
• Collaborate with logic designers to debug and resolve design issues, and work with software teams during bring-up and validation.
• Develop Perl, Python, and/or Shell scripts to improve verification infrastructure, automation, and methodology.

What you'll need

• Bachelor's or Master's degree in Electrical Engineering (BSEE/MSEE).
• 5+ years of experience in ASIC Verification.
• Strong experience with SystemVerilog for ASIC verification.
• Experience with constrained-random verification techniques.
• Hands-on experience with industry-standard verification methodologies such as OVM, VMM, or UVM.
• Proficiency in Perl, Tcl, Python, or Shell scripting.
• Strong problem-solving, debugging, and ASIC verification skills.
• Excellent analytical and collaboration skills.

Nice to have

• Perl/Tcl scripting preferred.
• Experience verifying networking protocols such as Ethernet.

Details

• Location: Bengaluru, Karnātaka, India.
• Work mode: Onsite, with an expectation of primarily working from an HPE office.