Video IP Design Verification Engineer

Overview

Define, model, design, verify, validate, implement and document IP (block/SoC) development for high performance, low power products, collaborating with cross-functional groups to determine the product execution path.

What you'll need

• Bachelor's degree in Science, Engineering, or related field.
• Looking for candidates between 3 to 13 years of experience.
• Worked on coverage driven module verification.
• Strong in System Verilog and UVM.
• Sound experience in testbench (stimulus, agent, monitor, checker) development.
• Failure debugging with Verdi and log files.
• Worked in verification with a C-based reference model inside the testbench.
• Experience with assertion development.
• Familiar with EDA tools IUS, VCS, Verdi etc.
• Exposure in scripting (Perl, Python).
• Good team player.
• Need to interact with designers and other verification engineers proactively.

Nice to have

• Prior experience with video pipeline.
• Knowledge of Tensilica.
• Worked with sub-system verification with Tensilica.
• Experience in C based system modelling.
• Debug with C based reference model.
• Exposure to other verification tasks: gate level simulation, power aware simulation, formal verification, sub-system verification and emulation.

Details

• Location: Bangalore, India.