Staff Engineer Verification -IP Digital Functional Verification

Overview

Lead IP/SoC verification activities for complex semiconductor designs, including developing verification environments and supporting multiple verification domains.

What you'll do

• Lead subtasks in IP/SoC verification.
• Contribute significantly to the verification of complex IPs/SoCs.
• Create IP/SoC-level verification requirements based on design requirements.
• Develop UVM test benches and formal verification environments.
• Support the development of verification infrastructure at the IP/chip level as required.
• Support RTL simulation, formal verification, power-aware verification, and gate-level simulation.

What you'll need

• Bachelor's degree (B.E./B.Tech.) in Electrical/Electronics Engineering or Master's degree (M.E./M.Tech.) in VLSI Design or a related field.
• Minimum 5+ years of relevant experience.
• Strong understanding of ASIC verification methodologies, concepts, and industry best practices.
• Proficiency in Verilog, SystemVerilog, and UVM with hands-on experience in verification environment development.
• Proven ability to develop and maintain IP and SoC-level testbenches for complex semiconductor designs.
• Experience in IP/SoC verification across a variety of applications and design domains.
• Strong analytical, debugging, and problem-solving skills, with the ability to work effectively in both independent and collaborative environments.
• Excellent communication and stakeholder collaboration skills, with a focus on delivering high-quality verification solutions.

Nice to have

• Knowledge of power-aware verification and gate-level verification (GLS).
• Familiarity with industry-standard protocols and interfaces.
• Exposure to formal verification techniques and tools.

Details

• Location: Bangalore BTP.