ASIC Engineer || Design Verification, UVM, Testbench || Exp- 8+ years

Overview

Design Verification Engineer focused on simulation and emulation of complex ASIC designs within Cisco Silicon One, owning verification strategy, test benches and coverage for networking hardware.

What you'll do

• Develop and implement verification plans and test benches using simulation tools and methodologies.
• Collaborate with design and validation teams to identify verification requirements and coverage goals.
• Utilize emulation platforms to run large-scale verification tests and debug design issues.
• Analyse verification results, identify bugs, and work closely with design engineers to resolve issues.
• Maintain and enhance verification infrastructure and automation frameworks.
• Document verification processes, test cases, and results to ensure traceability and reproducibility.
• Stay current with emerging verification technologies and best practices, particularly in emulation.
• Mentor junior engineers and contribute to team knowledge sharing.

What you'll need

• Bachelor's degree plus 7 years of related experience, or Master's degree plus 4 years of related experience, or PhD plus 1 year of related experience.
• Strong experience in design verification methodologies using UVM or OVM.
• Relevant experience in design verification with a strong emphasis on test methodologies.
• Experience with networking protocols such as Ethernet, AXI, AMBA, PCIe, etc.