Principal Verification Engineer

Overview

Own the verification of complex digital integrated circuits at the block, subsystem, or device level, ensuring compliance with specifications and error-free operation.

What you'll do

• Understand device requirements and functional descriptions to ensure compliance with specifications and error-free operation.
• Plan verification activities, develop testbenches, and execute tests.
• Develop verification platforms using the UVM methodology and SystemVerilog.
• Deliver verified designs at the device, subsystem or block level.
• Partner with a dedicated Design Lead to deliver high-confidence designs.
• Verify designs implemented in SystemVerilog RTL using industry-standard methodologies.
• Contribute to the development and enhancement of verification technologies and methodologies.
• Collaborate with Software and Validation teams to deliver devices that integrate into a wider system.
• Participate in Product Validation during the prototype stage of development.

What you'll need

• Bachelor's or Master's Degree in Electrical Engineering or Computer Engineering.
• 8+ years related experience.
• Excellent analytical and debugging skills and the ability to proactively solve issues.
• Proven ability to thrive on, learn and adapt to new methodologies and technologies.
• Strong coding skills.
• Experience using one or more of System Verilog/Verilog/VHDL, Tcl/Perl/Python, C/C++.
• Excellent verbal and written communication skills in English.
• Experience with verification methodologies, including UVM, formal verification, and constrained-random verification.

Details

• Location: Bangalore, India.
• Travel: 0% - 25%.