Senior Engineer - CPU Verification (RISCV Vector,ALU, FPU Verification)

Overview

Own verification planning and execution for the Vector, ALU and floating-point blocks of SiFive's RISC-V CPU cores, from test planning through unit-level verification and integration to core level.

What you'll do

• Own verification planning and execution for Vector, ALU and floating-point blocks, from test planning to unit-level verification and integration to core level.
• Drive verification strategy, test planning, testbench development, test writing, debug, coverage analysis, and closure for complex Vector, ALU and FPU execution-pipeline and datapath behaviours.
• Define effective verification approaches for arithmetic, floating-point, operand dependency, bypass/forwarding, replay, flush/recovery, exception, and execution-to-commit interactions.
• Develop robust verification environments, assertions, checkers, scoreboards, stimulus, and coverage models that expose corner cases and improve bug-finding efficiency.
• Partner closely with architecture, design, and verification teams to review specifications, identify risk early, and improve verification completeness.
• Drive efficient root-cause debug across specification, RTL, tests, and verification infrastructure.
• Contribute reusable methodology, automation, and infrastructure that improve verification quality and productivity across future CPU core programs.

What you'll need

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 4+ years of relevant experience in ASIC, CPU/core, or SoC design verification.
• Strong hands-on experience with SystemVerilog, UVM-based verification and modern verification methodologies.
• Solid understanding of computer architecture and CPU microarchitecture.
• Experience verifying one or more of the following areas: ALU pipelines, floating-point execution, datapath verification, formal verification, issue/dispatch behavior, dependency handling, forwarding, replay, or exception handling.
• Strong knowledge of verification flow methodology, including test planning, stimulus generation, debug, coverage analysis, and coverage closure.
• Good scripting or programming skills in Python, C/C++, or similar languages used for DV infrastructure and automation.

Nice to have

• Experience with high-performance out-of-order CPU core verification.
• Experience developing high-value assertions, checkers, and scoreboards for control-heavy or dependency-sensitive CPU behavior.
• Experience applying formal verification to execution logic, control interactions, or datapath correctness.
• Experience collaborating effectively across architecture, design, performance, and verification teams.

Details

• Location: Bengaluru, Karnataka, India.
• Requires a successful background and reference checks and satisfactory proof of right to work in India.
• Offer contingent on verification of authorization for access to export-controlled technology under applicable export control laws, or ability to obtain any necessary export license(s) or other approvals.