NOC DV Sr Engineer

Overview

Verification Architect/Engineer responsible for verifying next-generation infrastructure IPs (DDRSS, memory controllers, etc.) that go into SoCs for smartphones, tablets and other product categories.

What you'll do

• Own the DV test bench and associated collaterals (checkers, trackers, scoreboards, assertions, functional coverage).
• Develop test plans and test cases covering the design feature set; follow up with stakeholders on code coverage and functional coverage closure at different test bench levels.
• Plan and implement IP, cluster and formal verification flows for the infra IPs.
• Work closely with system architects, design and emulation teams on failure debug and code/functional coverage closure.
• Debug regression signatures and identify bug fixes.
• Develop and deploy scripts and tools for validation (Certitude, VC Formal, VPlan).
• Take responsibility for quality sign-off and required documentation.
• Debug and root-cause post-silicon issues in collaboration with design, software and test teams.
• Work with the SoC-level performance modeling team on latency and bandwidth analysis.
• Coordinate with different design and SoC teams throughout the IP development cycle.

What you'll need

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering or related field and 2+ years of Hardware Engineering or related work experience, OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering or related field and 1+ year of Hardware Engineering or related work experience, OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering or related field.
• Bachelor/Master's degree in Electronics & Communication / Micro Electronics.
• 3+ years of experience in IP verification or related.
• Strong debugging, analytical and problem-solving skills.
• Expertise in UVM-based verification.
• Knowledge of ARM bus protocols, virtual memory concepts and SoC system architecture.
• Experience developing monitors, scoreboards and sequencers using scripts, SystemVerilog, UVM and methodologies to speed up bug finding and resolution.
• Experience with UVM and ARM bus protocols.
• Communication and collaboration skills to work with a large worldwide design organization.

Nice to have

• Experience in designs optimized for low power (dynamic clock gating, logic/memory power collapse).
• Experience verifying designs meeting Automotive Safety Integrity Levels (ASIL).
• Proficiency in scripting languages (Python or Perl) for automation, and C/C++/SystemC for performance models.
• Post-silicon bring-up and HW-SW debug experience.
• Knowledge of and exposure to silicon debug tool chains.