NOC DV Sr Lead Engineer

Overview

Verification Architect/Engineer responsible for verifying next-generation Infrastructure IPs (DDRSS, Memory Controllers etc.) that go into System-on-chip (SoC) for smartphones, tablets and other product categories.

What you'll do

• Plan and implement IP/Cluster/Formal verification flows for the Infra IPs.
• Coordinate with different Design and SOC teams throughout the IP development cycle.
• Own DV test bench and associated collaterals (Checkers, Trackers, Scoreboards, Assertion, Functional Coverage).
• Develop test plan and test cases to cover design feature set, and follow up with stakeholders on code coverage and functional coverage closure at different levels of test bench.
• Work closely with System Architects, Design and emulation teams on failure debugs and code/functional coverage closure.
• Debug regression signatures and identify bug fixes.
• Responsible for Quality sign off and required documentation.
• Develop/deploy scripts/tools for validation (Certitude, VC Formal, VPlan).
• Debug and root cause post silicon issues in collaboration with Design, SW and test teams.
• Work with SoC level performance modeling team on latency and bandwidth analysis.

What you'll need

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience, OR Master's degree in the same fields and 2+ years of Hardware Engineering or related work experience, OR PhD in the same fields and 1+ year of Hardware Engineering or related work experience.
• Bachelor/Master's Degree in Electronics & Communication / Micro Electronics.
• 8 years of experience in IP verification or related.
• Experience with UVM and ARM Bus protocols.
• Strong debugging, analytical and problem-solving skills.
• Expertise in UVM based verification.
• Knowledgeable about ARM bus protocols, Virtual Memory concepts, SoC system architecture.
• Experience in developing Monitors, Scoreboards, Sequencers that utilize scripts, System Verilog, UVM, and methodologies to increase the rate at which bugs are found and resolved.
• Communication and collaboration skills to work with a large world-wide design organization.

Nice to have

• Experience in designs optimized for low power (dynamic clock gating, logic/memory power collapse).
• Experience in verifying designs meeting Automotive Safety Integrity Levels (ASIL).
• Proficiency in scripting languages (Python or Perl) for automation initiatives, and C/C++/SystemC for performance models.
• Post-si bring-up and HW-SW debug experience.
• Knowledge of and exposure to silicon debug tool chains.

Details

• Location: Bangalore, India.